Not true. The (add and subtract) operations use the same logic. Now, multiply and divide are a whole different kettle...

Really? I've -never- seen an IC chip that did subtraction directly. 'Adder' chips, however, are common as dirt.

You can -accomplish- subtraction using an 'adder' and a bunch of inverters on the second input (and ignore the overflow).

True 'subtract' logic

Subtraction: operand1 EQ operand2 => zero result, zero borrow operand1 EQ 1 AND operand2 EQ 0 => one result, zero borrow operand1 EQ 0 AND operand2 EQ 1 => one result, one borrow

To expound on the 'difference' between addition and subtraction, consider hardware that uses "ONES COMPLEMENT" arithmetic. Where the 'negative' of a number is represented by simply inverting all the bits of the positive value. e.g. the negative of "00000010" is "11111101".

Note well that in

It is

if you do it by 'actual' subtraction '00000011' -'00000011' ========== '00000000' which is 'positive zero', the desired result

To get the 'desired result' of 'positive zero', using

The 'does addition by complement and subtract' was

There are advantages to "1's complement" over "2's complement", notably

On the other side of the fence, there

On Apr 13, 4:40 pm, snipped-for-privacy@host122.r-bonomi.com (Robert Bonomi) wrote:

Really. Really? You haven't looked very hard. http://www.onsemi.com/pub_link/Collateral/MC10H180-D.PDF

...which are the same operations.

So what? Are you trying to prove your prowess with useless information?

<snipped useless '1's complement stuff>

Really. Really? You haven't looked very hard. http://www.onsemi.com/pub_link/Collateral/MC10H180-D.PDF

...which are the same operations.

So what? Are you trying to prove your prowess with useless information?

<snipped useless '1's complement stuff>

Are you showing off that the information is useless to YOU because your prowess is so elevated?

Idiot. A particular method of encoding negative numbers isn't relevant when discussing the difference/similarity between subtraction and addition. I wouldn't expect you to know anything about it. OTOH, you are up to your usual standards in cashing checks with your mouth that you ass can't cover.

Idiot. A particular method of encoding negative numbers isn't
relevant when

FWIW, and I won't wish to get dragged into any muck, the algorithm for performing of translating to negative numbers (assuming 2s complement representation) IS relevant if one will evaluate expressions of the form A-B as A+(-B).

Since bitwise negation can be performed by a single transistor, I would expect that that a value in a register could be negated VERY fast. I think just a few clock cycles.

Bill

FWIW, and I won't wish to get dragged into any muck, the algorithm for performing of translating to negative numbers (assuming 2s complement representation) IS relevant if one will evaluate expressions of the form A-B as A+(-B).

Since bitwise negation can be performed by a single transistor, I would expect that that a value in a register could be negated VERY fast. I think just a few clock cycles.

Bill

Only if you're doing invert-add to perform subtraction. The topic was specifically about hardware subtraction (or addition = complement- subtract),

Above you use 2's complement representations in your example. Now you switch tracks to 1's complement representation of negative numbers (the only format where negation = inversion). Yes, bitwise

Above you use 2's complement representations in your example. Now you switch tracks to 1's complement representation of negative numbers (the only format where negation = inversion). Yes, bitwise

That must be one of the reasons they switched to 2s complement, no?

I hate to answer my own question, but the main reason was the duplicity of zeros in 1s complement, I think.

Bill

Mainly, but the uncertainty of the wrap-around-carry doesn't help. I mot sure whether some of the fancier adders (carry look-ahead, carry save, etc.) work well for 1's complement, either (again, the wrap-around issue). Your observation on the two zeros is spot on, however. That takes an additional operation in the critical path of most calculations.

The 'ambiguous' bit-pattern for 'zero'

For

At the vehement urging of the makers of 'budget' computing systems, as well as the users thereof, 2's complement arithmetic was selected for the IEEE standard,

I

data showed that only in ***VERY***RARE*

I think some would say that if your variables are getting close to their limits very often, then it's time to consider looking for a new data structure.

I think some would say that if your variables are getting close to their limits very often, then it's time to consider looking for a new data structure.

The "standard' algorithm, in computer

Yup. on a 2's complement machine, "NOT" (1's complement negate) is

Yup, you're one of 'them' alright. You ain't much.

What a moron, RoboTwat, but I already knew that.

Yup, you're right to the core. I find it interesting that the bulk of your comments are degrading and condescending to justabout anybody here. You must really think you're something. Welll... I'm here to tell you that you are not nice.

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