OT-ish: resistor value solver

[The Natural Philosopher]

Sometimes they are..;-)

How else did Clive Sinclair make his first pile?

a few years back. When did YIOU?

You haven;'t worked for small companies much either, have you?

[The Natural Philosopher]

And you wouldn't get far in any manufacturing team designing like that.

IF you can get away with it, fine. You are safe, but its needlessly restrictive, and costs more money, and prevents quite useable clock speeds being achieeved.

[pete]

Wasn't it with "cheapo" audio amplifiers? I also seem to remember a flat loudspeaker - though that may have been someone else.

[Bob Eager]

There was the Quad Electrostatic.

[Fredxx]

I can cite a thousand designs which use absolute component tollearances, and which have never used monte carlo methods.

These do not sound like off the shelf components to me. But it is interesting that you accept the "top and bottom tails chopped off" and if the spec included 2 duff ones then why would you expect anything different? Generally most specs don't allow the occasional duff ones to get through, which implies you were talking of a rather dated research contract.

Generally yes, but the process has test structures to ensure the process is in spec. When they're out of spec, they either get moved into a lower spec bin or trashed. Device key timing and other behavioural paprameters are usually individually tested. Occasioanlly some are claimed to be within tolerance by design. Either way the accpetance criteria is defined.

Generally most resistors are of the surface mount variety. I doubt they have spiral grouves.

I agree, that is the art of design. Generally 10% can be used, but where 1% resistors are ordered, then that is what I expect to receive, possibly even a "clipped" gaussian curve. They may even have a "hole" in the value curve, where high precsion 0.1% or similar have been selected.

"Of course not"! I didn't think so. A tolerance on a datasheet is just that, a specification which by default is individually tested.

[pete]

Oh no - the one I'm thinking of looked like a polystyrene ceiling tile (might even have sounded like one, too) and was about that size.

[<me9]

Micro alloy transistors, Manufacturer's rejects sold at a premium.

[Frank Erskine]

On Thu, 10 Sep 2009 23:15:00 +0100, had this to say:

I think you're thinking of Ian Sinclair. Was he any relation to Clive?

Sinclair did make a small flattish loudspeaker, about a foot square and only an inch or so thick. Obviously it wasn't all that high quality, but it was quite neat and sufficed for average background music and announcements - a bit better than the traditional railway-style "tannoy" system.

[Man at B&Q]

Let's leave the cowboys out of it.

As manufactured, the spread of resistor value, achievable clock speed, etc may well be a guassian curve or some other curve. We're talking about components as chosen by and delivered to customers were absolute tolerances apply, unless tha manufacturer states otherwise. E.g. 1% resistors will be +/-1% of the stated value with some distribution of values within that band.

Very often and very recently. There is no statistics involved, just cumulative worst case min and max delays.

Tin pot outfits that don't know what they're doing? No.

MBQ

[The Natural Philosopher]

nah..before that he sold rebadged throwaway reject Neewmarket Transistors as pukka wunderful stuff for hobbyists.

[The Natural Philosopher]

No it was a Sinciqalr. Made of styrene foam.

[The Natural Philosopher]

No, it was Clive.

[Man at B&Q]

Manufacturing teams (in semiconductors) are not heavily involved in the design of what they ultimately make, unless something goes very wrong. They will run test wafers and they will contiinually monitor the process. Results of that monitoring may well be analysed statistically and the results used to tweak the process.

Designers use timing models supplied by the foundry/library vendor for the process they have specified. Thise timing models are used cummulatively to calculate worst case delays. You simply cannot make any assumptions about gaussian or any other distribution of delays within a single devices.

Individual devices will vary with some distribution of performance. They are sorted during wafer probe and test into those that simply don't work due to defects, those that can be repaired if the design includes redundancy and then into different grades, e.g. clock speed or access time depending on the device. Some will still fail at this stage being either too fast or too slow. As time goes on and the process is tweaked the defect rate goes down and the distribution of devices changes.

Customers are supplied with devices with known performance e.g. "this processor will run at 2GHz", not "here's 10,000,000 processors with a spread of performance from 1.8 to 2.4 GHz".

MBQ

[dennis]

A conspiracy (there are a few of those in diy ATM) to get people used to DAB and mp3 quality.

[dennis]

I have to agree. If you are designing stuff for production you have to work out the min and max for the chain and adjust the design as required so that it will work whatever stock part is fitted. Select on test is a big no-no. It can be a real swine when the manufacturer changes their process and the same device no longer has the same hold and setup times as that can bugger up a design that has been working for years. I had one that stopped working for that precise reason and the design had to be changed to register some inputs that didn't need to be registered when the state machine was initial designed.

[The Natural Philosopher]

The stochastic analysis is in the CHIP design.

The CHIP is then tested to see where it may e.g. be clocked. Ones that fail to clock at one speed are derated to be sold for low clock speed applications.

Where the kids then overclock, to fine tune their performabnce to the bleeding edge of relaibility ;-)

You are already making and assumption that they are no worse than the manufacturer says they are.

Which they may well be..occasionally.

Remember my expertise goes back to the says before LSI, to design with individual small components. That sort of expertise is now only applicable to chip design., not the simplistic assembly of other peoples designs on the PCB of choice and a bit of firmware.

You may well be able to use worst case analysis on that and not lose money. There are, after all, very few components of any real significance.

Analogue design of complex circuits with many components was, I can assure you, a matter of finding a balance between wishful statistical analysis and a given reject rate off the production line.

Precisely. The DESIGN of those chips is done on a certain probability of failure, and those that do fail are binned or re-labelled.

You cant exactly control doping levels no matter how hard you try or ensure total homogeneity of the substrate.

To design for worst case is to create a chip that always pases, and is needlessly over engineered.

I suspect the difference here, is that what I call design, is not what you call design. Throwing 5 of someone elses chips on a board with a few support discrete components is not design as far as I am concerned.

I am talking about 3-4000 components on half a dozen boards 3each one of which would be analagous to a single chip in terms of complexity.

I am talking about discrete components, resistors and capacitors and semiconductors with but three legs. these are all supplied with brioadly gaussian distributions with truncated tails.

and in large quantities and complex circuits, can be analysed stochastically. And are.

The general effect of combining N elements of gaussian distribution about a mean, is to create a probability distribution of similar shape, but much narrower spread. It still has the tails going out as far, but they are much thinner tails.

I accept that when doing all that on a single piece of silicon, there may be correlation in performance between the elements, which lessens the effect.BUT its still there.

And its used. The more RANDOM (e.g. gausian) performance of e.g. time delay elements there are in a chain, the more the overall delay will tend to the sum of the means. And the less examples outside the tolerance there will be.

[Man at B&Q]

Maybe we're talking at cross purposes but you were the one who said "IF you can get away with it, fine. You are safe, but its needlessly restrictive, and costs more money, and prevents quite useable clock speeds being achieeved" which kind of implies digital logic.

Analyse all you like. Can you provide an example of *design* that assumes a guassian distribution of component value/performance rather than designing around it?

Theer *is* correlation. There will be small differences, but they are not used during the design of the logic to be implemented on the chip. The timimg models used during design are already worst case.

No it isn't.

Any such effect is not accounted for during design of the logic. Worst case delays are added and subtracted cumulatively. There's no statistical tinkering when calculating propogation delays or set-up and hold time margins. The only time statistics are involved is when determining MTBF when sampling asynchronous signals.

MBQ

[The Natural Philosopher]

any chip you buy.

[Man at B&Q]

So WTF are you talking about? "discrete components, resistors and capacitors and semiconductors with but three legs. these are all supplied with brioadly gaussian distributions with truncated tails" as you asserted a little way back up the thread, or chips? Please make your mind up.

Perhaps I should have asked for an example of the *design process* that assumes a guassian distribution of component value/performance rather than designing around it?

MBQ

[Fredxx]

You're not living in the real world of electronics. Component have a nominal performance (gaussian spread) but also a pass / fail criteria. They are tested over the extremes of temperature, timings and speeds, and indeed a significant porportion of the cost of an IC is in its measurement. After testing the component is then graded according to speed and temperature and pricing is often according to yield.

What and when was the last piece of equipement you designed?